1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method of a semiconductor device and, more particularly, to a semiconductor device having a ferroelectric capacitor and a method of manufacturing the same.
2. Description of the Related Art
As the nonvolatile memory that can store the information after a power supply is turned OFF, the flash memory and the ferroelectric memory (FeRAM) are known.
The flash memory has the floating gate that is buried in the gate insulating film of the insulated-gate field effect transistor (IGFET), and stores the information by accumulating the charge representing the stored information in the floating gate. In order to write/erase the information, a tunnel current that passes through the gate insulating film must be supplied, and thus a relatively high voltage is required.
The FeRAM has the ferroelectric capacitor that stores the information by utilizing the hysteresis characteristic of the ferroelectric substance. In the ferroelectric capacitor, the ferroelectric film formed between the upper electrode and the lower electrode generates the polarization in response to the voltage applied between the upper electrode and the lower electrode, and has the spontaneous polarization that maintains the polarization even after the applied voltage is removed.
If the polarity of the applied voltage is inverted, the polarity of the spontaneous polarization is also inverted. The information can be read out by sensing the polarity and the magnitude of the spontaneous polarization. The FeRAM has such an advantage that such FeRAM can operate at a lower voltage than the flash memory and can perform the high-speed writing with low power consumption.
The capacitor employed in the memory cell of the FeRAM has such a structure that, as set forth in following Patent Literatures 1 to 3, the PZT film, for example, is employed as the ferroelectric film and also the ferroelectric film is put between the upper electrode and the lower electrode. The platinum film, for example, is employed as the lower electrode, and also the platinum film, the iridium oxide film, or the like, for example, is employed as the upper electrode.
In Patent Literature 1, the oxidized titanium adhesive layer is formed on the thermal oxide film that covers the CMOS integrated circuit wafer, and the platinum lower electrode layer, the PZT ferroelectric film, and the iridium upper electrode layer are formed sequentially on the titanium adhesive layer.
In Patent Literature 2, it is described that the Si3N4 surface layer, the Al2O3 intermediate layer, the platinum layer, and the PZT ferroelectric layer are formed sequentially on the silicon wafer. According to this, it is concluded that the PZT ferroelectric layer, which has the uniform layer structural body rather than the case where the material containing the titanium is employed as the intermediate layer, can be formed. In this case, the Al2O3 intermediate layer is formed at the temperature of 100 to 300° C. by the sputtering.
In Patent Literature 3, it is described that the ferroelectric capacitor constructed by sequentially forming the first hydrogen barrier film, the Pt lower electrode film, the PZT film, the Pt upper electrode film, and the second hydrogen barrier film is formed on the insulating film, whereby the characteristic deterioration of the ferroelectric capacitor can be suppressed. Also, it is described that, as the hydrogen barrier film, at least one type is selected from meta oxides consisting of aluminum oxide (Al2O3), AlxOy, AlN, WN, SrRuO3, IrOx, RuOx, ReOx, OsOx, MgOx, ZrOx, etc.
[Patent Literature 1]
Specification of US Patent Application Publication 2002/0074601
[Patent Literature 2]
Pamphlet of International Publication No. 98/05062
[Patent Literature 3]
Patent Application Publication (KOKAI) 2001-36026
Although the underlying film made of either the titanium-containing material film or the metal oxide is formed under the lower electrode in above Patent Literatures 1 to 3, this method cannot sufficiently improve the characteristic of the ferroelectric capacitor and cannot suppress variation in the performances of the memory cells of the same chip.